The invention relates to a true flash analog-to-digital converter (ADC) for digital systems requiring fastest possible high resolution conversion of an analog input signal into a corresponding digital output code.
The conventional true N-bit flash ADCs comprise a reference source, K comparators connected in parallel and a chain of K (mostly K+1) equally valued resistors providing reference voltages thereto, wherein K=2.sup.N -1. An encoder samples the comparator output signals, corrects faulty codes and provides binary output code. All ADCs are clocked.
The true flash ADCs offer the fastest possible conversion as the input signal is converted into the output code in just one cycle. In particular, no feedback manipulating the input signal is used as the quantization level thereof is determined in a straightforward structure. Moreover, the conversion of the input signal into the digital form is performed in a most simple manner and by just one type of component, i.e. comparator. Digital pipelining is often used to boost sampling rates.
The conventional flash ADCs do suffer however from many problems, mostly originating from inaccuracy or complexity of the comparators. In particular, the employment of the required number of comparators having a poor accuracy results in missing codes. Generally, comparators with bipolar input stage have smaller input error voltages. However, the input bias currents are very high and vary with the input signal. The bias currents are added so that different resistors of the resistor network conduct different currents. Thereby, the reference signals provided by the network are unstable and resistor values must be small. Moreover, the respective bipolar transistors require high collector currents as to achieve short transition times. As a result, the ADCs consume a large amount of power and a relatively low resolution is achievable.
FETs are generally faster than bipolar transistors and have input currents practically equal zero. However, FET input comparators have a very poor accuracy. Autozeroing comparators are necessary which however significantly increase the circuit complexity and reduce the conversion speed. As a result, the flash ADCs based on FET comparators have a higher resolution and improved power consumption. The conversion speed which is the main objective of flash ADCs is diminished. The resistor network is still necessary.
The resistor network is unavoidable in conventional flash ADCs and causes deficient long term and temperature stability, reduced speed and accuracy, enlarged chip space and increased power consumption, etc. In contrast, integrated MOS capacitors are most accurate integrated circuit components. For instance, their absolute accuracy and tolerance fluctuation due to time, mechanical stress and voltage are far superior to any other component.
The poor accuracy and complexity of the comparators as well as the performance of the resistor network result in missing codes. Certain kinds of errors caused by a false response of the comparators are not possible to correct thru a digital correction in the encoder, wherein a final error is large. For instance, the flash ADCs have a tendency to miss a code every few billion conversions, i.e. several times a minute when ADC is sampling at 100 MHz.